Conference Program

18:00 – 20:00 Welcome Reception & Registration
Bierstube "Fritze", Hotel Dorint (conference hotel)
8:00 Registration
9:00 Welcome

Keynote 1 - chair: Ivan Sutherland

10:30 Coffee Break

Paper Session 1: Error Resilience

chair: Jakob Lechner

  • Naoya Onizawa, Shoun Matsunaga and Takahiro Hanyu
    A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure
  • Guangda Zhang, Wei Song, Jim Garside, Javier Navaridas and Zhiying Wang
    An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults
12:00 Lunch

Industrial Paper & Fresh Ideas Session 1: Metastability

chair: Ian Jones

  • Salomon Beer, Marco Cannizzaro, Jordi Cortadella, Ran Ginosar and Luciano Lavagno
    Metastability in Better-Than-Worst-Case Designs
  • Fresh Ideas: Mohammed Alshaikh, Gordon Russell and Alex Yakovlev
    Level-Shifting Handshake Synchronizer
  • Fresh Ideas: Marco Cannizzaro, Solomon Beer, Jordi Cortadella, Ran Ginosar and Luciano Lavagno
    SafeRazor: metastability-robust Aadaptive clocking in resilient circuits
15:00 Coffee Break

Industrial Paper Session 2: Design and Test

chair: Ken Stevens

  • Mike Davies, Andrew Lines, Jon Dama, Alain Gravel, Robert Southworth, Georgios Dimou and Peter Beerel
    A 72-Port 10G Ethernet Switch/Router using Quasi-Delay-Insensitive Asynchronous Design
  • Gang Wang, Xu Wang, Xinke Chen and Shuangbai Xue
    Test and Repair Flow for Shared BISR in Asynchronous Multi-Processors
  • Marc Renaudin, Aurélien Buhrig, Charles Guillemet, Robin Wilson and Sylvain Engels
    Clockless Design Performance Monitoring for Nanometer Technologies
  • Arash Saifhashemi, Dylan Hand, Peter Beerel, William Koven and Hong Wang
    Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis
17:30 Closure

Keynote 2 - chair: Ivan Sutherland

09:30 Coffee Break

Paper Session 2: Interfacing Fundamentals

chair: Mika Nyström

  • Danil Sokolov and Alex Yakovlev
    GALS partitioning by behavioural decoupling expressed in Petri nets
  • Graham Birtwistle and Kenneth Stevens
    Modelling Mixed 4phase Pipelines: Structures and Patterns

Paper Session 3: Established Applications

chair: Tomohiro Yoneda

  • Joycee Mekie
    Effect of Dynamic Frequency Scaling on Interface Design for Rationally-Related Multi-Clocked Systems
  • Evangelia Kasapaki and Jens Sparsø
    Argo: A Time-Elastic Time-Division-Multiplexed NOC using Asynchronous Routers
12:00 Lunch

Paper Session 4: Asynchronous Design Automation

chair: Hong Chen

  • Matheus Moreira, Ney Calazans, Mayler Martins, Augusto Neutzler, Andre Reis and Renato Ribas
    Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?
  • Fu-Chiung Cheng, Yuan-Feng Chen, Shu-Chuan Huang and Ching Yang Huang
    Synthesis of QDI FSMs from Synchronous Specifications
  • Mehrdad Najibi and Peter Beerel
    Integrated Fanout Optimization and Slack Matching of Asynchronous Circuits
14:45 Coffee Break

Fresh Ideas Session 2: Novel Applications

chair: Erik Brunvand

  • Xin Fan, Steffen Peter and Milos Krstic
    From Old Ideas to New Questions – Exploring GALS Design for SCA Resistance Multi-Clocked Systems
  • Tong Lin, Joseph Chang and Tong Ge
    A Fully-Printed Asynchronous RFID Tag with a Novel Delay-Insensitive Load Modulation Scheme
  • Marvin Faix, Emmanuel Mazer and Laurent Fesquet
    An Asynchronous CMOS Probabilistic Computer idea
16:15 Short Break

Fresh Ideas Session 3: Asynchronous Facts You Thought You Knew… But Do You?

chair: Erik Brunvand

  • William Koven, Prasad Joshi and Peter Beerel
    Performance Yield Benefits of Asynchronous Design in a High Variability Environment
  • Mika Nyström
    A Surprisingly Delay-Insensitive Circuit
17:05 Closure
18:00 Social Event & Banquet
Boat trip covering 7 lakes surrounding Potsdam with a view on historical and natural attractions. Includes a buffet dinner with local German culinary specialties, on the boat.
22:00 End of Social Event

Keynote 3 - chair: Ivan Sutherland, Alex Yakovlev

10:00 Coffee Break

Paper Session 5 & Fresh Ideas Session 4: Low Power

chair: Edith Beigné

  • Arash Saifhashemi, Hsin-Ho Huang and Peter Beerel
    Reconditioning: Automatic Power Optimization of QDI Circuits
  • Benjamin Tang, Sunil Bhave and Rajit Manohar
    Low Power Asynchronous VLSI with NEM Relays
  • Fresh Ideas: Alex Yakovlev, Haider Alrudainy and Andrey Mokhov
    Balancing Regularity and Burstiness in Architecting New Computer Systems
12:00 Lunch

Paper Session 6 & Fresh Ideas Session 5: Tools and Libraries

chair: Peter Beerel

  • Matheus Moreira, Michel Arendt, Ricardo Guazzelli and Ney Calazans
    A New CMOS Topology for Low Voltage Null Convention Logic Gates Design
  • Fresh Ideas: Frederico Butzke, Chris Myers, Matheus Moreira and Ney Calazans
    QDI Logic for Signaling Data Validity in Bundled-Data Design: A Kogge-Stone Case Study
  • Fresh Ideas: Norman Kluge and Ralf Wollowski
    Completing the Resynthesis Flow for Balsa Circuits by Focusing on the Data Path – first Experiments



chair: Moisés Herrera

  • Moisés Herrera and Francisco Viveros
    Asynchronous Circuits Mapped on Programmable Logic Devices
  • Mahdi Jelodari Mamaghani, Will Toms, Andrew Bardsley and Jim Garside
    Exploiting Synchrony for Area and Performance Improvement in the Asynchronous Domain
  • Matheus Moreira, Michel Arendt, Adriel Ziesemer, Ricardo Reis and Ney Calazans
    Automated Synthesis of Cell Libraries for Semi-Custom Asynchronous Design
  • Maxim Rykunov, Andrey Mokhov, Danil Sokolov, Alex Yakovlev
    POWERPROP: Asynchronous Design for Power Proportionality
16:00 Best Paper Award & Closure